1. Field of the Invention
The present invention relates to a bit synchronizing circuit used in a receiver for high speed serial communication represented by the IEEE 1394, the ATM (asynchronous transfer mode), the space light communication or the like.
2. Description of the Related Art
Along with digitization of an information apparatus, high speed serial communication of digital signals have been widely used for applications ranging from data transfer between LSIs to radio communication or optical fiber commutation.
In such digital communication, it is necessary to send timing information for sampling data correctly in addition to communication data. In many cases, high speed serial communication does not use a separate line for the timing information from the line for the data in order to maintain a low number of communication lines. Instead, the data is made to have a redundancy and coding is used so that the data is securely transferred within a certain cycle of time. Because the transfer of the data itself is the timing information, the data can be correctly recovered, based on the transfer of the data, on the receiver end in the case where the intervals between the transfers are short enough. A circuit to realize this is called a bit synchronizing circuit or a symbol synchronization circuit.
In recent years in high speed serial communication a system called burst mode communication for sending and receiving data intermittently such as a time division system of a dual line type subscriber line system in ISDN (integrated services digital network) and other types of half duplex communication have been developed. In burst mode communication a particular pattern called a preamble is usually transferred before the data to be transferred is transferred in order to establish bit synchronization. Because the data to be transferred cannot be sent during the cycle of the preamble, the shorter the preamble is the more effective the communication is. To shorten the preamble it is important for the technology of the bit synchronizing circuit to establish synchronization at high speed.
Furthermore, in the case of such a system as to convert signals using an amplifier such as optical fiber communication or radio communication, a bias may arise in the pulse width of the signals until the amplifier is stabilized. A signal waveform of the transmission and reception when that phenomenon occurs is shown in FIG. 10. In FIG. 10, the transmitted signal represents changes in outputs of the transmitter with time. In FIG. 10 is shown a repetitive pattern of 0 and 1 used frequently as a preamble. For example, in the case of optical fiber communication, an LED or laser outputs optical signals based on this transmitted signal.
The received signal as shown in FIG. 10 is an example of a signal which is amplified and processed after a light signal is received by a light receiving element. Depending on the characteristics of the amplifier or the like on the reception end, the cycle where the signal is high becomes long as compared to the transmitted signal while the cycle of low is shortened at the lead of received signal. This tendency becomes smaller while continuing the reception of the signal, which gradually approaches to a waveform of the transmitted signal. To eliminate the influence of the bias of this received signal, it is necessary to further add a preamble. In order to correspond to such a case, a bit synchronizing circuit becomes important to carry out correct synchronization even in the case where the pulse width is biased.
As for prior art to gain such a bit synchronization the following six types are known.
A first technology uses a PLL (phase-locked loops) as disclosed in “Phase-Locked Loops—Design, Simulation, and Applications” Third Edition, Roland E. Best, 1997, McGraw-Hill. In this technology a voltage-controlled oscillator is used to generate a clock on the reception end. The voltage-controlled oscillator is of such a type that outputted clock rate can be changed by changing the operating voltage. The PLL controls the rate of the voltage-controlled oscillator so that the transfer point of the received signal and the transfer point of the clock coincide by using the phase difference between the transfer point of the received signal and the generated clock. In this way, by sampling the received data, with the clock synchronized with the received signal, the signals can be correctly received.
In general, the bit synchronizing circuit which generates a clock synchronized with a received signal on the reception end is generally called a clock recovery system. In the case where the clock recover system is applied for the bit synchronizing circuit, since the received data is synchronized with the clock synchronized with the received signal, an asynchronous FIFO (first in first out) is usually used so as to synchronize the received data with the system clock to the receiver. The received signal is written into the asynchronous FIFO with the clock synchronized with the received signal and by reading out with the system clock of the receiver, it possible to have a synchronization with the system clock of the receiver.
A second technology uses a high speed clock which samples data with a significantly fast clock compared to the bit rate and which determines the sample timing for reception according to the timing of change in sample data value. The UART (universal asynchronous receiver and transmitter) which is a serial controller of a PC uses this method. In the UART a data format called an asynchronousness is used. Usually, in the asynchronousness a start bit is added in the front and a stop bit is added at the end for each eight bits of data. The start bit is always 1 while the stop bit is always 0. The received signal is sampled with a clock of 16 times the bit rate and at the time point when the sample data changes from 0 to 1, that is to say, when the start bit begins, the 4 bit counter is initialized. The sample data when the counter turns to 8 is stored for 8 times so as to confirm that the next stop bit is 0 to be outputted as received data.
A third technology uses switching of two oscillators as described in Japanese Unexamined Patent Publication JP-A 6-53950 (1994). Following the high and low of the received signal, the operation of two oscillators are alternatively started with the operation. The two oscillators start the operation at the surge or the drop of the received signal, respectively, therefore their outputs are synchronized with the received signal. By taking OR of the outputs of the two oscillators, a clock synchronized with the received data is generated. In this technology the asynchronous FIFO described in the first technology is also necessary.
A fourth technology uses a polyphase clock selecting method which selects a polyphase clock, that is, a clock with the closest phase to that of the received data among a plurality of clocks with shifted phases as disclosed in Japanese Unexamined Patent Publication JP-A 7-193562 (1995), Japanese Unexamined Patent Publication JP-A 9-181713 (1997), Japanese Unexamined Patent Publication JP-A 10-247903 (1998). In those publications, a mounting method for selecting a clock with the closest phase to the transfer point of the received signal among a plurality of clocks is disclosed. In this technology the asynchronous FIFO described in the first technology is also necessary.
A fifth technology attempts to accelerate the rate of asynchronousness as disclosed in “A CMOS Serial Link for Fully Duplexed Data Communication,” K. Lee, et al., IEEE Journal of Solid-State Circuits, Vol. 30, No. 4, April 1995. In this technology a polyphase clock with a speed of one tenth of the bit rate is used so as to enhance parallelization to implement high speed communication of 500 Mbps. More concretely, 40 clocks of one tenth with equally shifted phases are used. By re-sampling the data sampled by those clocks with a single clock, the information equal to that gained by sampling the duration of a 10 bit time with a rate four times as fast as the bit rate can be gained with intervals of 50 MHz.
By inputting the data to an edge detection circuit, a changing point from 0 to 1 is detected. Actually this technology presumes that to transmit a preamble in the form of 1111100000 in front of the data to be sent at least three times, and during this term, only one part for one time of sampling, that is to say, only at the lead of the start bit changes from 0 to 1. Thereby, it is possible to specify the position of the start bit. Even after the data starts to be transmitted and received after the preambles are finished, the edge of the start bit emerges at almost the same part and, therefore, a circuit is incorporated so that the edge within the data is ignored and the edge of the start bit is trailed.
As described above, the position of the edge of the start bit can be specified while receiving the data, 4 samples each from there are regarded as corresponding to each bit. A value of each bit is determined by a majority decision of the corresponding 4 samples.
A sixth technology uses an over-sampling as disclosed in Japanese Unexamined Patent Publication JP-A 9-36849 (1997). In this technology, the result of sampling the received signal with a faster rate than the bit rate is parallelized at the same rate as the bit rate in order to gain the data, which is then processed. More concretely, changing points are sampled from parallel data to select sample data regarded as reception data from the number and the position of changing points within the parallel data.
However, there exist the following problems with the above described first to sixth technologies.
In the first technology, since it takes time for the synchronization, a long preamble is necessary in front of the data. Additionally because the first technology includes an analog circuit, it is difficult to mass-produce at low cost.
In the second technology, in the case of high speed communication of 100 Mbps to a few Gbps, a clock frequency of several hundreds MHz or more is required, which is not suitable for mounting in an inexpensive CMOS LSI.
In the third technology since the clock is instantaneously synchronized with the edge of the data, the fluctuation of the received signal directly leads to the fluctuation of the clock as it is. In the case where the fluctuation is large, it is necessary to operate the asynchronous FIFO at high speed which is required for the clock recovery system.
According to the fourth technology, from the edge information of the received signal a clock is selected and the received signal is sampled with the selected clock, which needs to be adjusted precisely considering the delay of the circuit selecting the clock. This delay adjustment is accompanied by the same difficulty of the production as that of an analog circuit.
According to the fifth technology only the transition of the STOP/START bit is trailed and the transition is not considered for the data bit part. That is to say, since the transition at the data bit part is not as timing information, there are cases where correction may not be carried out for the fluctuation of the received signal. And since it is determined by majority selection, there are cases where the pulse width of 0 and 1 tends to become biased to either side which can not be coped with.
The fifth technology samples the received signal which is not in a synchronous relationship with a polyphase clock. Usually a D flip-flop is used for the sampling. In order to operate the D flip-flop normally the inputted data need to be held at a constant value for a certain period of time before and after the clock. In the case where the inputted data is not held at a constant value for this period of time, there is the possibility that the D flip-flop may output an unstable value which is neither 0 nor 1. This phenomenon is called metastability. The metastability causes a malfunction of the circuit, therefore, it is desirable to reduce the possibility of occurrence. In the fifth technology this problem is coped with by connecting the sense amplifier in a form or a four stage cascade.
In the sixth technology, the output of the received data is fixed to the clock rate of the receiver, which is inefficient against fluctuation or errors of the bit rate, therefore, it is difficult to maintain the synchronization for a long period of time.
As described above, the conventional methods have defects, and therefore it becomes a problem to be solved to implement bit synchronization which satisfies as many items in the following as possible:                (a) synchronization at high speed,        (b) maintaining the synchronization,        (c) few or no analog parts,        (d) elimination of asynchronous FIFO of high speed,        (e) elimination of clock of high speed,        (f) strong resistance to fluctuation of received signals,        
(g) countermeasure against the bias of a particular waveform.